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digic6:registers [2025/05/05 19:10] – [Setting palette for Indexed RGB layers] kitordigic6:registers [2025/05/05 19:14] (current) – kitor
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 ^ Offset ^ Summary          ^ Description ^ ^ Offset ^ Summary          ^ Description ^
 | +0     | Flags            | Configures data type, transformations (flip, upscale), zebras, etc | | +0     | Flags            | Configures data type, transformations (flip, upscale), zebras, etc |
-| +0x4   | Vram index ?     | Assignment to a peviously registered Vram buffer ID |+| +0x4   | Vram index ?     | Assignment to a previously registered Vram buffer ID |
 | +0x8   | Input offsets    | Source buffer offsets (skips). ''x_off | (y_off << 16)'' | | +0x8   | Input offsets    | Source buffer offsets (skips). ''x_off | (y_off << 16)'' |
 | +0xC   | Vram resolution  | Source buffer size in pixels. ''width | (height << 16)'' | | +0xC   | Vram resolution  | Source buffer size in pixels. ''width | (height << 16)'' |
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 === Vram index === === Vram index ===
  
-Wildly enough, MMIO doesn't take source buffer address, but rather a number associated to VRAM, which is registered via different MMIO. See TBD.+Wildly enough, MMIO doesn't take source buffer address, but rather a number associated to VRAM, which is registered via different MMIO. See [[registers##vram_registration|Vram registration]].
  
 Vram index register seems to also take two 16 bit values instead of one, possibly for layers that use separate image and alpha buffers (eg UYVY+AA, unconfirmed). Vram index register seems to also take two 16 bit values instead of one, possibly for layers that use separate image and alpha buffers (eg UYVY+AA, unconfirmed).
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-^ Base address   ^ Generation  +^ Base address   ^ Generation ^ 
-| ''0xD2030100'' | DIGIC 6 +| ''0xD2030100'' | DIGIC 6 | 
-| ''0xD2060040'' | DIGIC 7+| ''0xD2060040'' | DIGIC 7 |
  
 MMIO structure is as below: MMIO structure is as below:
  
-^ Offset ^ Summary     ^ Description +^ Offset ^ Summary     ^ Description ^ 
-| +0x0   | index       | Numerical ID, 8 bits - used for assignment in HW layer registers. +| +0x0   | index       | Numerical ID, 8 bits - used for assignment in HW layer registers. | 
-| +0x4   | pitch ?     | Derivative of image width. Computed as ''(( width << 16) >> 20) - 1 | 0x20000'' +| +0x4   | pitch ?     | Derivative of image width. Computed as ''(( width << 16) >> 20) - 1 | 0x20000'' | 
-| +0x8   | pointer-ish | Vram address bit shifted 8 to the right. Possibly to enforce alignment.+| +0x8   | pointer-ish | Vram address bit shifted 8 to the right. Possibly to enforce alignment. |
  
 MMIO as to be written in order, be aware of any compiler optimizations (best to set data structures as volatile). MMIO as to be written in order, be aware of any compiler optimizations (best to set data structures as volatile).
digic6/registers.1746465021.txt.gz · Last modified: 2025/05/05 19:10 by kitor