Differences

This shows you the differences between two versions of the page.

--- digic6:registers [2025/05/05 19:09] – [Hardware compositor / layers] kitor
+++ digic6:registers [2025/05/05 19:14] (current) – kitor
@@ Line 24: / Line 24: @@
 ^ Offset ^ Summary          ^ Description ^
 | +0     | Flags            | Configures data type, transformations (flip, upscale), zebras, etc |
-| +0x4   | Vram index ?     | Assignment to a peviously registered Vram buffer ID |
+| +0x4   | Vram index ?     | Assignment to a previously registered Vram buffer ID |
 | +0x8   | Input offsets    | Source buffer offsets (skips). ''x_off | (y_off << 16)'' |
 | +0xC   | Vram resolution  | Source buffer size in pixels. ''width | (height << 16)'' |
@@ Line 34: / Line 34: @@
 === Vram index ===
-Wildly enough, MMIO doesn't take source buffer address, but rather a number associated to VRAM, which is registered via different MMIO. See TBD.
+Wildly enough, MMIO doesn't take source buffer address, but rather a number associated to VRAM, which is registered via different MMIO. See [[registers##vram_registration|Vram registration]].
 Vram index register seems to also take two 16 bit values instead of one, possibly for layers that use separate image and alpha buffers (eg UYVY+AA, unconfirmed).
@@ Line 96: / Line 96: @@
-^ Base address   ^ Generation
+^ Base address   ^ Generation ^
-| ''0xD2030100'' | DIGIC 6
+| ''0xD2030100'' | DIGIC 6 |
-| ''0xD2060040'' | DIGIC 7
+| ''0xD2060040'' | DIGIC 7 |
 MMIO structure is as below:
-^ Offset ^ Summary     ^ Description
+^ Offset ^ Summary     ^ Description ^
-| +0x0   | index       | Numerical ID, 8 bits - used for assignment in HW layer registers.
+| +0x0   | index       | Numerical ID, 8 bits - used for assignment in HW layer registers. |
-| +0x4   | pitch ?     | Derivative of image width. Computed as ''(( width << 16) >> 20) - 1 | 0x20000''
+| +0x4   | pitch ?     | Derivative of image width. Computed as ''(( width << 16) >> 20) - 1 | 0x20000'' |
-| +0x8   | pointer-ish | Vram address bit shifted 8 to the right. Possibly to enforce alignment.
+| +0x8   | pointer-ish | Vram address bit shifted 8 to the right. Possibly to enforce alignment. |
 MMIO as to be written in order, be aware of any compiler optimizations (best to set data structures as volatile).
@@ Line 135: / Line 135: @@
 This works differently than Digic 5 and below. There's a MMIO structure (per output), which takes a pointer to palette of 256 uint32_t entries stored in RAM.
-^ Address        ^ Output
+^ Address        ^ Output ^
-| ''0xD2010680'' | HDMI
+| ''0xD2010680'' | HDMI |
-| ''0xD20139A0'' | LCD
+| ''0xD20139A0'' | LCD |
-| ''?''          | Video
+| ''?''          | Video |
 MMIO structure is as below:
-^ Offset ^ Summary     ^ Description
+^ Offset ^ Summary     ^ Description ^
-| +0x0   | apply       | Write 0x1 to apply selected palette
+| +0x0   | apply       | Write 0x1 to apply selected palette |
-| +0x4   | flag maybe  | Unknown, Canon BL writes 0xFF
+| +0x4   | flag maybe  | Unknown, Canon BL writes 0xFF |
-| +0x8   | pointer-ish | Palette address, bit shifted 4 to the right. Possibly to enforce alignment.
+| +0x8   | pointer-ish | Palette address, bit shifted 4 to the right. Possibly to enforce alignment. |
 Please note that fields has to be written in order: flag, pointer, apply.