====== DIGIC X ======

===== Interrupt Vector Table: =====

^ Vector ^ Description ^
| 0x000 | -noise-                        |
| 0x001 | EDOMAIN_EDMAC_1_WR_M1          |
| 0x002 | EDOMAIN_EDMAC_6_WR_SS7         |
| 0x003 | EDOMAIN_EDMAC_3_RD_S1_A        |
| 0x004 | EDOMAIN_VITON1                 |
| 0x005 | (reserved)                     |
| 0x006 | (reserved)                     |
| 0x007 | CPROC_14                       |
| 0x008 | TMU_INT_SWA                    |
| 0x009 | TMU_INT_OCCH0SP                |
| 0x00a | INTC_XINT_0                    |
| 0x00b | TCU_T0OUT                      |
| 0x00c | POSTMAN_RCVINT0                |
| 0x00d | POSTMAN_FIFOINT0               |
| 0x00e | MARIUS_TIMER_OC0_INT           |
| 0x00f | MARIUS_TIMER_IC0_INT           |
| 0x010 | EDOMAIN_SYNGEN_1               |
| 0x011 | EDOMAIN_EDMAC_1_WR_S0          |
| 0x012 | EDOMAIN_EDMAC_6_WR_SS8         |
| 0x013 | EDOMAIN_EDMAC_3_RD_L0_B        |
| 0x014 | EDOMAIN_VITON2                 |
| 0x015 | (reserved)                     |
| 0x016 | (reserved)                     |
| 0x017 | CPROC_15                       |
| 0x018 | TMU_INT_SWB                    |
| 0x019 | TMU_INT_OCCH0EP                |
| 0x01a | INTC_XINT_1                    |
| 0x01b | TCU_T1OUT                      |
| 0x01c | POSTMAN_RCVINT1                |
| 0x01d | POSTMAN_FIFOINT1               |
| 0x01e | MARIUS_TIMER_OC1_INT           |
| 0x01f | MARIUS_TIMER_IC1_INT           |
| 0x020 | EDOMAIN_SYNGEN_2               |
| 0x021 | EDOMAIN_EDMAC_1_WR_S1          |
| 0x022 | EDOMAIN_EDMAC_6_WR_SS9         |
| 0x023 | EDOMAIN_EDMAC_3_RD_L1_B        |
| 0x024 | EDOMAIN_AFFINE_OVR_ERR         |
| 0x025 | (reserved)                     |
| 0x026 | (reserved)                     |
| 0x027 | SYNC_IRQ_LSS1                  |
| 0x028 | TMU_INT_OCALL                  |
| 0x029 | TMU_INT_OCCH1SP                |
| 0x02a | INTC_XINT_2                    |
| 0x02b | TCU_T2OUT                      |
| 0x02c | POSTMAN_RCVINT2                |
| 0x02d | POSTMAN_FIFOINT2               |
| 0x02e | MARIUS_TIMER_OC2_INT           |
| 0x02f | MARIUS_TIMER_IC2_INT           |
| 0x030 | EDOMAIN_SYNGEN_3               |
| 0x031 | EDOMAIN_EDMAC_1_WR_S2          |
| 0x032 | EDOMAIN_EDMAC_7_WR_S0          |
| 0x033 | EDOMAIN_EDMAC_3_RD_S0_B        |
| 0x034 | EDOMAIN_SARIDON                |
| 0x035 | (reserved)                     |
| 0x036 | (reserved)                     |
| 0x037 | SYNC_IRQ_LSS1_ST1              |
| 0x038 | TMU_INT_PULGENCEI              |
| 0x039 | TMU_INT_OCCH1EP                |
| 0x03a | INTC_XINT_3                    |
| 0x03b | TCU_T3OUT                      |
| 0x03c | POSTMAN_RCVINT3                |
| 0x03d | POSTMAN_FIFOINT3               |
| 0x03e | MARIUS_TIMER_OC3_INT           |
| 0x03f | MARIUS_TIMER_IC3_INT           |
| 0x040 | EDOMAIN_SYNGEN_4               |
| 0x041 | EDOMAIN_EDMAC_1_WR_S3          |
| 0x042 | EDOMAIN_EDMAC_7_WR_S1          |
| 0x043 | EDOMAIN_EDMAC_3_RD_S1_B        |
| 0x044 | EDOMAIN_MESSI                  |
| 0x045 | (reserved)                     |
| 0x046 | (reserved)                     |
| 0x047 | SYNC_IRQ_LSS2                  |
| 0x048 | TMU_INT_ICAPCEI                |
| 0x049 | TMU_INT_OCCH2SP                |
| 0x04a | INTC_XINT_4                    |
| 0x04b | TCU_T4OUT                      |
| 0x04c | POSTMAN_RCVINT4                |
| 0x04d | POSTMAN_FIFOINT4               |
| 0x04e | MARIUS_TIMER_OC4_INT           |
| 0x04f | MARIUS_TIMER_IC4_INT           |
| 0x050 | EDOMAIN_SYNGEN_FRM             |
| 0x051 | EDOMAIN_EDMAC_1_WR_S4          |
| 0x052 | EDOMAIN_EDMAC_7_WR_SS0         |
| 0x053 | EDOMAIN_EDMAC_5_RD_L0          |
| 0x054 | EDOMAIN_DURAN                  |
| 0x055 | (reserved)                     |
| 0x056 | (reserved)                     |
| 0x057 | SYNC_IRQ_LSS2_ST1              |
| 0x058 | CPROC_0                        |
| 0x059 | TMU_INT_OCCH2EP                |
| 0x05a | INTC_XINT_5                    |
| 0x05b | TCU_T5OUT                      |
| 0x05c | POSTMAN_RCVINT5                |
| 0x05d | POSTMAN_FIFOINT5               |
| 0x05e | MARIUS_TIMER_OC5_INT           |
| 0x05f | MARIUS_TIMER_IC5_INT           |
| 0x060 | EDOMAIN_SYNGEN_1_A             |
| 0x061 | EDOMAIN_EDMAC_1_WR_SS0         |
| 0x062 | EDOMAIN_EDMAC_7_CAP_WR_SS0     |
| 0x063 | EDOMAIN_EDMAC_5_RD_M0          |
| 0x064 | EDOMAIN_DANCING_FEN            |
| 0x065 | (reserved)                     |
| 0x066 | (reserved)                     |
| 0x067 | SYNC_IRQ_INTVI1                |
| 0x068 | CPROC_1                        |
| 0x069 | TMU_INT_OCCH3SP                |
| 0x06a | INTC_XINT_6                    |
| 0x06b | TCU_IPCOUT4                    |
| 0x06c | POSTMAN_RCVINT6                |
| 0x06d | POSTMAN_FIFOINT6               |
| 0x06e | MARIUS_TIMER_OC6_INT           |
| 0x06f | MARIUS_TIMER_IC6_INT           |
| 0x070 | EDOMAIN_SYNGEN_2_A             |
| 0x071 | EDOMAIN_EDMAC_1_WR_SS1         |
| 0x072 | EDOMAIN_EDMAC_7_CAP_WR_SS1     |
| 0x073 | EDOMAIN_EDMAC_5_RD_M1          |
| 0x074 | EDOMAIN_DANCING_SURF           |
| 0x075 | (reserved)                     |
| 0x076 | (reserved)                     |
| 0x077 | SYNC_IRQ_VI1_SET_1             |
| 0x078 | CPROC_2                        |
| 0x079 | TMU_INT_OCCH3EP                |
| 0x07a | INTC_XINT_7                    |
| 0x07b | TCU_T4F_INT                    |
| 0x07c | POSTMAN_RCVINT7                |
| 0x07d | POSTMAN_FIFOINT7               |
| 0x07e | MARIUS_TIMER_OC7_INT           |
| 0x07f | MARIUS_TIMER_IC7_INT           |
| 0x080 | EDOMAIN_SYNGEN_3_A             |
| 0x081 | EDOMAIN_EDMAC_1_WR_SS2         |
| 0x082 | EDOMAIN_EDMAC_7_CAP_WR_SS2     |
| 0x083 | EDOMAIN_EDMAC_5_RD_S0          |
| 0x084 | EDOMAIN_DANCING_RACI           |
| 0x085 | FDOMAIN_0                      |
| 0x086 | SYNC_IRQ_INTB60V               |
| 0x087 | SYNC_IRQ_VI1_SET_2             |
| 0x088 | CPROC_3                        |
| 0x089 | TMU_INT_OCCH4SP                |
| 0x08a | INTC_XINT_8                    |
| 0x08b | TCU_IPCOUT5                    |
| 0x08c | POSTMAN_DIRECTINT0             |
| 0x08d | POSTMAN_SEMAPHORE0             |
| 0x08e | MARIUS_TIMER_ICOC_OC0INT       |
| 0x08f | MARIUS_TIMER_ICOC_IC0INT       |
| 0x090 | EDOMAIN_SYNGEN_4_A             |
| 0x091 | EDOMAIN_EDMAC_1_WR_SS3         |
| 0x092 | EDOMAIN_EDMAC_0_OPERA_WR       |
| 0x093 | EDOMAIN_EDMAC_5_RD_S1          |
| 0x094 | EDOMAIN_KOALA_WR0              |
| 0x095 | FDOMAIN_1                      |
| 0x096 | SYNC_IRQ_INTB59V               |
| 0x097 | SYNC_IRQ_VI1_SET_3             |
| 0x098 | CPROC_4                        |
| 0x099 | TMU_INT_OCCH4EP                |
| 0x09a | INTC_XINT_9                    |
| 0x09b | TCU_T5F_INT                    |
| 0x09c | POSTMAN_DIRECTINT1             |
| 0x09d | POSTMAN_SEMAPHORE1             |
| 0x09e | MARIUS_TIMER_ICOC_OC1INT       |
| 0x09f | MARIUS_TIMER_ICOC_IC1INT       |
| 0x0a0 | EDOMAIN_SYNGEN_FRM_A           |
| 0x0a1 | EDOMAIN_EDMAC_1_WR_SS4         |
| 0x0a2 | EDOMAIN_EDMAC_6_DAN_WR         |
| 0x0a3 | EDOMAIN_EDMAC_5_RD_S2          |
| 0x0a4 | EDOMAIN_KOALA_WR1              |
| 0x0a5 | FDOMAIN_2                      |
| 0x0a6 | SYNC_IRQ_INTB50V               |
| 0x0a7 | SYNC_IRQ_INTVI2                |
| 0x0a8 | CPROC_5                        |
| 0x0a9 | TMU_INT_OCCH5SP                |
| 0x0aa | INTC_XINT_10                   |
| 0x0ab | APROC_0                        |
| 0x0ac | POSTMAN_DIRECTINT2             |
| 0x0ad | POSTMAN_SEMAPHORE2             |
| 0x0ae | OMAR_TIMER_OC0_INT             |
| 0x0af | OMAR_TIMER_IC0_INT             |
| 0x0b0 | EDOMAIN_SYNGEN_1_B             |
| 0x0b1 | EDOMAIN_EDMAC_2_WR_L0_A        |
| 0x0b2 | EDOMAIN_EDMAC_1_RD_L0          |
| 0x0b3 | EDOMAIN_EDMAC_6_RD_S0          |
| 0x0b4 | EDOMAIN_KOALA_WR2              |
| 0x0b5 | FDOMAIN_3                      |
| 0x0b6 | SYNC_IRQ_INTB49V               |
| 0x0b7 | SYNC_IRQ_VI2_SET_1             |
| 0x0b8 | CPROC_6                        |
| 0x0b9 | TMU_INT_OCCH5EP                |
| 0x0ba | INTC_XINT_11                   |
| 0x0bb | APROC_1                        |
| 0x0bc | POSTMAN_DIRECTINT3             |
| 0x0bd | POSTMAN_SEMAPHORE3             |
| 0x0be | OMAR_TIMER_OC1_INT             |
| 0x0bf | OMAR_TIMER_IC1_INT             |
| 0x0c0 | EDOMAIN_SYNGEN_2_B             |
| 0x0c1 | EDOMAIN_EDMAC_2_WR_L1_A        |
| 0x0c2 | EDOMAIN_EDMAC_1_RD_L1          |
| 0x0c3 | EDOMAIN_EDMAC_6_RD_S1          |
| 0x0c4 | EDOMAIN_KOALA_RD0              |
| 0x0c5 | FDOMAIN_4                      |
| 0x0c6 | SYNC_IRQ_INTL60V1              |
| 0x0c7 | SYNC_IRQ_VI2_SET_2             |
| 0x0c8 | CPROC_7                        |
| 0x0c9 | TMU_INT_ICAPCH0                |
| 0x0ca | INTC_XINT_12                   |
| 0x0cb | APROC_2                        |
| 0x0cc | POSTMAN_DIRECTINT4             |
| 0x0cd | POSTMAN_FIFO_ERR0              |
| 0x0ce | OMAR_TIMER_OC2_INT             |
| 0x0cf | OMAR_TIMER_IC2_INT             |
| 0x0d0 | EDOMAIN_SYNGEN_3_B             |
| 0x0d1 | EDOMAIN_EDMAC_2_WR_S0_A        |
| 0x0d2 | EDOMAIN_EDMAC_1_RD_L2          |
| 0x0d3 | EDOMAIN_EDMAC_6_RD_S2          |
| 0x0d4 | EDOMAIN_KOALA_RD1              |
| 0x0d5 | FDOMAIN_5                      |
| 0x0d6 | SYNC_IRQ_INTL60V1_ST1          |
| 0x0d7 | SYNC_IRQ_VI2_SET_3             |
| 0x0d8 | CPROC_8                        |
| 0x0d9 | TMU_INT_ICAPCH1                |
| 0x0da | INTC_XINT_13                   |
| 0x0db | APROC_3                        |
| 0x0dc | POSTMAN_DIRECTINT5             |
| 0x0dd | UART0_RX_INTREQRX              |
| 0x0de | OMAR_TIMER_OC3_INT             |
| 0x0df | OMAR_TIMER_IC3_INT             |
| 0x0e0 | EDOMAIN_SYNGEN_4_B             |
| 0x0e1 | EDOMAIN_EDMAC_2_WR_L0_B        |
| 0x0e2 | EDOMAIN_EDMAC_1_RD_M0          |
| 0x0e3 | EDOMAIN_EDMAC_6_RD_S3          |
| 0x0e4 | EDOMAIN_KOALA_RD2              |
| 0x0e5 | FDOMAIN_6                      |
| 0x0e6 | SYNC_IRQ_INTL60V2              |
| 0x0e7 | SYNC_IRQ_INTVI3                |
| 0x0e8 | CPROC_9                        |
| 0x0e9 | TMU_INT_ICAPCH2                |
| 0x0ea | INTC_XINT_14                   |
| 0x0eb | APROC_4                        |
| 0x0ec | POSTMAN_DIRECTINT6             |
| 0x0ed | UART0_TX_INTREQTX              |
| 0x0ee | OMAR_TIMER_OC4_INT             |
| 0x0ef | OMAR_TIMER_IC4_INT             |
| 0x0f0 | EDOMAIN_SYNGEN_FRM_B           |
| 0x0f1 | EDOMAIN_EDMAC_2_WR_L1_B        |
| 0x0f2 | EDOMAIN_EDMAC_1_RD_S0          |
| 0x0f3 | EDOMAIN_EDMAC_6_RD_S4          |
| 0x0f4 | EDOMAIN_COMBAT_INTEG_1         |
| 0x0f5 | FDOMAIN_7                      |
| 0x0f6 | SYNC_IRQ_INTL60V2_ST1          |
| 0x0f7 | SYNC_IRQ_VI3_SET_1             |
| 0x0f8 | CPROC_10                       |
| 0x0f9 | TMU_INT_ICAPCH3                |
| 0x0fa | INTC_XINT_15                   |
| 0x0fb | APROC_5                        |
| 0x0fc | POSTMAN_DIRECTINT7             |
| 0x0fd | UART1_RX_INTREQRX              |
| 0x0fe | OMAR_TIMER_OC5_INT             |
| 0x0ff | OMAR_TIMER_IC5_INT             |
| 0x100 | EDOMAIN_HEAD_ERR               |
| 0x101 | EDOMAIN_EDMAC_2_WR_S0_B        |
| 0x102 | EDOMAIN_EDMAC_1_RD_S1          |
| 0x103 | EDOMAIN_EDMAC_6_RD_S5          |
| 0x104 | EDOMAIN_COMBAT_BLOCK_1         |
| 0x105 | FDOMAIN_8                      |
| 0x106 | SYNC_IRQ_INTL59V1              |
| 0x107 | SYNC_IRQ_VI3_SET_2             |
| 0x108 | CPROC_11                       |
| 0x109 | TMU_INT_ICAPCH4                |
| 0x10a | INTC_XINT_16                   |
| 0x10b | APROC_6                        |
| 0x10c | CCLIME_INT_SODA                |
| 0x10d | UART1_TX_INTREQTX              |
| 0x10e | OMAR_TIMER_OC6_INT             |
| 0x10f | OMAR_TIMER_IC6_INT             |
| 0x110 | EDOMAIN_ATOMIC_ERR             |
| 0x111 | EDOMAIN_EDMAC_3_WR_L0_A        |
| 0x112 | EDOMAIN_EDMAC_1_RD_SS0         |
| 0x113 | EDOMAIN_EDMAC_6_RD_S6          |
| 0x114 | EDOMAIN_COMBAT_INTEG_7         |
| 0x115 | (reserved)                     |
| 0x116 | SYNC_IRQ_INTL59V1_ST1          |
| 0x117 | SYNC_IRQ_VI3_SET_3             |
| 0x118 | CPROC_12                       |
| 0x119 | TMU_INT_ICAPCH5                |
| 0x11a | INTC_XINT_17                   |
| 0x11b | APROC_7                        |
| 0x11c | CCLIME_INT_TM2MD_RDMA          |
| 0x11d | UART2_RX_INTREQRX              |
| 0x11e | OMAR_TIMER_OC7_INT             |
| 0x11f | OMAR_TIMER_IC7_INT             |
| 0x120 | EDOMAIN_HEAD_ERR2              |
| 0x121 | EDOMAIN_EDMAC_3_WR_S0_A        |
| 0x122 | EDOMAIN_EDMAC_1_RD_SS1         |
| 0x123 | EDOMAIN_EDMAC_6_RD_S7          |
| 0x124 | EDOMAIN_COMBAT_BLOCK_7         |
| 0x125 | (reserved)                     |
| 0x126 | SYNC_IRQ_INTL59V2              |
| 0x127 | SYNC_IRQ_INTVI4                |
| 0x128 | CPROC_13                       |
| 0x129 | TMU_INT_ICAPCH6                |
| 0x12a | INTC_XINT_18                   |
| 0x12b | APROC_8                        |
| 0x12c | CCLIME_INT_TM2MD_WDMA          |
| 0x12d | UART2_TX_INTREQTX              |
| 0x12e | OMAR_TIMER_ICOC_OC0INT         |
| 0x12f | OMAR_TIMER_ICOC_IC0INT         |
| 0x130 | EDOMAIN_HEAD_ERR3              |
| 0x131 | EDOMAIN_EDMAC_3_WR_S1_A        |
| 0x132 | EDOMAIN_EDMAC_1_RD_SS2         |
| 0x133 | EDOMAIN_EDMAC_6_RD_S8          |
| 0x134 | EDOMAIN_WEABER1                |
| 0x135 | ORCA_A_0                       |
| 0x136 | SYNC_IRQ_INTL59V2_ST1          |
| 0x137 | SYNC_IRQ_VI4_SET_1             |
| 0x138 | CPROC_16                       |
| 0x139 | TMU_INT_ICAPCH7                |
| 0x13a | INTC_XINT_19                   |
| 0x13b | APROC_9                        |
| 0x13c | CCLIME_INT_TSUMXD_RDMAC        |
| 0x13d | PCIE_IRQ_PCIE0                 |
| 0x13e | OMAR_TIMER_ICOC_OC1INT         |
| 0x13f | OMAR_TIMER_ICOC_IC1INT         |
| 0x140 | EDOMAIN_SAP1                   |
| 0x141 | EDOMAIN_EDMAC_3_WR_L0_B        |
| 0x142 | EDOMAIN_EDMAC_1_RD_SS3         |
| 0x143 | EDOMAIN_EDMAC_6_RD_SS0         |
| 0x144 | EDOMAIN_WEABER2                |
| 0x145 | ORCA_A_1                       |
| 0x146 | SYNC_IRQ_INTL50V1              |
| 0x147 | SYNC_IRQ_VI4_SET_2             |
| 0x148 | CPROC_17                       |
| 0x149 | TMU_INT_ICAPCH8                |
| 0x14a | INTC_XINT_20                   |
| 0x14b | (reserved)                     |
| 0x14c | CCLIME_INT_TSUMXD_W0DMA        |
| 0x14d | PCIE_IRQ_PCIE1                 |
| 0x14e | REM_REM_INT                    |
| 0x14f | ZICO_TIMER_IRQ                 |
| 0x150 | EDOMAIN_SAP2                   |
| 0x151 | EDOMAIN_EDMAC_3_WR_S0_B        |
| 0x152 | EDOMAIN_EDMAC_1_RD_SS4         |
| 0x153 | EDOMAIN_EDMAC_6_RD_SS1         |
| 0x154 | EDOMAIN_HISTORY                |
| 0x155 | ORCA_A_2                       |
| 0x156 | SYNC_IRQ_INTL50V1_ST1          |
| 0x157 | SYNC_IRQ_VI4_SET_3             |
| 0x158 | CPROC_18                       |
| 0x159 | TMU_INT_ICAPCH9                |
| 0x15a | INTC_XINT_21                   |
| 0x15b | (reserved)                     |
| 0x15c | CCLIME_INT_TSUMXD_W1DMA        |
| 0x15d | PCIE_IRQ_PCIE2                 |
| 0x15e | SDDOMAIN_SDCON0                |
| 0x15f | HDMAC0_INTRREQ1                |
| 0x160 | EDOMAIN_LIP                    |
| 0x161 | EDOMAIN_EDMAC_3_WR_S1_B        |
| 0x162 | EDOMAIN_EDMAC_1_RD_SS5         |
| 0x163 | EDOMAIN_EDMAC_6_RD_SS2         |
| 0x164 | EDOMAIN_HISTORY2_1             |
| 0x165 | ORCA_A_3                       |
| 0x166 | SYNC_IRQ_INTL50V2              |
| 0x167 | SYNC_IRQ_INTVI4B               |
| 0x168 | (reserved)                     |
| 0x169 | TMU_INT_ICAPCH10               |
| 0x16a | INTC_XINT_22                   |
| 0x16b | (reserved)                     |
| 0x16c | CCLIME_INT_CPU_SLEEP           |
| 0x16d | PCIE_IRQ_PCIE3                 |
| 0x16e | SDDOMAIN_TDMAC0                |
| 0x16f | HDMAC0_INTRREQ2                |
| 0x170 | EDOMAIN_SANTA1                 |
| 0x171 | EDOMAIN_EDMAC_5_WR_M0          |
| 0x172 | EDOMAIN_EDMAC_1_RD_SS6         |
| 0x173 | EDOMAIN_EDMAC_6_RD_SS3         |
| 0x174 | EDOMAIN_HISTORY2_2             |
| 0x175 | ORCA_A_4                       |
| 0x176 | SYNC_IRQ_INTL50V2_ST1          |
| 0x177 | SYNC_IRQ_VI4B_SET_1            |
| 0x178 | (reserved)                     |
| 0x179 | TMU_INT_ICAPCH11               |
| 0x17a | INTC_XINT_23                   |
| 0x17b | (reserved)                     |
| 0x17c | CCLIME_INT_OTHERS              |
| 0x17d | PCIE_IRQ_PCIE4                 |
| 0x17e | SDDOMAIN_SDCON1                |
| 0x17f | HDMAC0_INTRREQ3                |
| 0x180 | EDOMAIN_YAWARA                 |
| 0x181 | EDOMAIN_EDMAC_5_WR_S0          |
| 0x182 | EDOMAIN_EDMAC_2_RD_L0_A        |
| 0x183 | EDOMAIN_EDMAC_6_RD_SS4         |
| 0x184 | EDOMAIN_HISTORY2_3             |
| 0x185 | ORCA_A_5                       |
| 0x186 | SYNC_IRQ_INTLSSDV1             |
| 0x187 | SYNC_IRQ_VI4B_SET_2            |
| 0x188 | (reserved)                     |
| 0x189 | TMU_INT_SWA_ONLY               |
| 0x18a | INTC_XINT_24                   |
| 0x18b | HERMES_SITTER                  |
| 0x18c | CCLIME_INT_UART1_RX            |
| 0x18d | PCIE_IRQ_PCIE5                 |
| 0x18e | SDDOMAIN_TDMAC1                |
| 0x18f | HDMAC0_INTRREQ4                |
| 0x190 | EDOMAIN_OPERA_OPEKICK0         |
| 0x191 | EDOMAIN_EDMAC_5_WR_S1          |
| 0x192 | EDOMAIN_EDMAC_2_RD_L1_A        |
| 0x193 | EDOMAIN_EDMAC_6_RD_SS5         |
| 0x194 | EDOMAIN_HISTORY2_4             |
| 0x195 | ORCA_A_6                       |
| 0x196 | SYNC_IRQ_INTLSSDV1_ST1         |
| 0x197 | SYNC_IRQ_VI4B_SET_3            |
| 0x198 | SYNC_IRQ_VI6_SET_3             |
| 0x199 | TMU_INT_SWB_ONLY               |
| 0x19a | INTC_XINT_25                   |
| 0x19b | HERMES_SWEET                   |
| 0x19c | CCLIME_INT_UART1_TX            |
| 0x19d | USB_INT_TENG                   |
| 0x19e | SDDOMAIN_SDCON2                |
| 0x19f | HDMAC0_INTRREQ5                |
| 0x1a0 | EDOMAIN_OPERA_OPEKICK1         |
| 0x1a1 | EDOMAIN_EDMAC_5_WR_S2          |
| 0x1a2 | EDOMAIN_EDMAC_2_RD_S0_A        |
| 0x1a3 | EDOMAIN_EDMAC_6_RD_SS6         |
| 0x1a4 | EDOMAIN_BIKING                 |
| 0x1a5 | ORCA_A_7                       |
| 0x1a6 | SYNC_IRQ_INTLSSDV2             |
| 0x1a7 | SYNC_IRQ_INTVI5                |
| 0x1a8 | SYNC_IRQ_INTVI7                |
| 0x1a9 | TMU_INT_SWC_ONLY               |
| 0x1aa | INTC_XINT_26                   |
| 0x1ab | HERMES_SWAN0                   |
| 0x1ac | CCLIME_INT_TSUM_SD_SDCON       |
| 0x1ad | DSI0_IRQ_DSI0                  |
| 0x1ae | SDDOMAIN_TDMAC2                |
| 0x1af | HDMAC0_INTRREQ6                |
| 0x1b0 | EDOMAIN_OPERA_OPEKICK2         |
| 0x1b1 | EDOMAIN_EDMAC_6_WR_S0          |
| 0x1b2 | EDOMAIN_EDMAC_2_RD_S1_A        |
| 0x1b3 | EDOMAIN_EDMAC_6_RD_SS7         |
| 0x1b4 | EDOMAIN_CAPTAIN                |
| 0x1b5 | ORCA_A_8                       |
| 0x1b6 | SYNC_IRQ_INTLSSDV2_ST1         |
| 0x1b7 | SYNC_IRQ_INTVI6                |
| 0x1b8 | SYNC_IRQ_VI7_SET_1             |
| 0x1b9 | TMU_INT_SWD_ONLY               |
| 0x1ba | INTC_XINT_27                   |
| 0x1bb | HERMES_SWAN1                   |
| 0x1bc | CCLIME_INT_TSUM_SD_DMA         |
| 0x1bd | DSI1_IRQ_DSI1                  |
| 0x1be | DMA330_0                       |
| 0x1bf | HDMAC0_INTRREQ7                |
| 0x1c0 | EDOMAIN_OPERA_OPEKICK3         |
| 0x1c1 | EDOMAIN_EDMAC_6_WR_S1          |
| 0x1c2 | EDOMAIN_EDMAC_2_RD_S2_A        |
| 0x1c3 | EDOMAIN_EDMAC_6_RD_SS8         |
| 0x1c4 | EDOMAIN_COTTON                 |
| 0x1c5 | ORCA_A_9                       |
| 0x1c6 | SYNC_IRQ_INTP                  |
| 0x1c7 | SYNC_IRQ_VI6_SET_1             |
| 0x1c8 | SYNC_IRQ_VI7_SET_2             |
| 0x1c9 | (reserved)                     |
| 0x1ca | INTC_IRQ_SOFT_OUT              |
| 0x1cb | HERMES_DUAL_CTRL               |
| 0x1cc | CCLIME_INT_CITRON_CORE         |
| 0x1cd | HDMI0_0                        |
| 0x1ce | DMA330_1                       |
| 0x1cf | MDOMAIN_0                      |
| 0x1d0 | EDOMAIN_OPERA_OPEKICK4         |
| 0x1d1 | EDOMAIN_EDMAC_6_WR_S2          |
| 0x1d2 | EDOMAIN_EDMAC_2_RD_S3_A        |
| 0x1d3 | EDOMAIN_EDMAC_7_RD_S0          |
| 0x1d4 | EDOMAIN_OPERA0                 |
| 0x1d5 | ORCA_A_10                      |
| 0x1d6 | SYNC_IRQ_INTP_ST1              |
| 0x1d7 | SYNC_IRQ_VI6_SET_2             |
| 0x1d8 | SYNC_IRQ_VI7_SET_3             |
| 0x1d9 | (reserved)                     |
| 0x1da | (reserved)                     |
| 0x1db | ALGS_0                         |
| 0x1dc | CCLIME_INT_CITRON_RDMA         |
| 0x1dd | HDMI0_1                        |
| 0x1de | DMA330_2                       |
| 0x1df | MDOMAIN_1                      |
| 0x1e0 | EDOMAIN_OPERA_OPEKICK5         |
| 0x1e1 | EDOMAIN_EDMAC_6_WR_S3          |
| 0x1e2 | EDOMAIN_EDMAC_2_RD_L0_B        |
| 0x1e3 | EDOMAIN_EDMAC_7_CAP_RD_SS0     |
| 0x1e4 | EDOMAIN_OPERA_ERR0             |
| 0x1e5 | ORCA_B_11                      |
| 0x1e6 | SYNC_IRQ_INTE                  |
| 0x1e7 | SSIO_SSIOINT                   |
| 0x1e8 | SYNC_IRQ_INTVIO                |
| 0x1e9 | (reserved)                     |
| 0x1ea | (reserved)                     |
| 0x1eb | ALGS_1                         |
| 0x1ec | CCLIME_INT_CITRON_WDMA         |
| 0x1ed | HDMI1_0                        |
| 0x1ee | DMA330_3                       |
| 0x1ef | MDOMAIN_2                      |
| 0x1f0 | EDOMAIN_OPERA_OPEKICK6         |
| 0x1f1 | EDOMAIN_EDMAC_6_WR_S4          |
| 0x1f2 | EDOMAIN_EDMAC_2_RD_L1_B        |
| 0x1f3 | EDOMAIN_EDMAC_0_OPERA_RD       |
| 0x1f4 | EDOMAIN_OPERA_ABORT0           |
| 0x1f5 | ORCA_B_12                      |
| 0x1f6 | SYNC_IRQ_INTE_ST1              |
| 0x1f7 | SIO0_SIO0INT                   |
| 0x1f8 | SYNC_IRQ_VIO_SET_1             |
| 0x1f9 | (reserved)                     |
| 0x1fa | (reserved)                     |
| 0x1fb | (reserved)                     |
| 0x1fc | CCLIME_RESERVED                |
| 0x1fd | HDMI1_1                        |
| 0x1fe | (reserved)                     |
| 0x1ff | MDOMAIN_3                      |
| 0x200 | EDOMAIN_EDMAC_1_WR_L0          |
| 0x201 | EDOMAIN_EDMAC_6_WR_SS0         |
| 0x202 | EDOMAIN_EDMAC_2_RD_S0_B        |
| 0x203 | EDOMAIN_EDMAC_6_DAN_RD         |
| 0x204 | EDOMAIN_OPERA1                 |
| 0x205 | ORCA_B_13                      |
| 0x206 | DOLPHIN_IRQ_DOLPHIN_0          |
| 0x207 | SIO1_SIO1INT                   |
| 0x208 | SYNC_IRQ_VIO_SET_2             |
| 0x209 | (reserved)                     |
| 0x20a | (reserved)                     |
| 0x20b | (reserved)                     |
| 0x20c | CCLIME_SLOTC_SDDAT1_INT        |
| 0x20d | SROMC0_OCTAL_IRQ               |
| 0x20e | I2C0_TIRQ                      |
| 0x20f | MDOMAIN_4                      |
| 0x210 | EDOMAIN_EDMAC_1_WR_L1          |
| 0x211 | EDOMAIN_EDMAC_6_WR_SS1         |
| 0x212 | EDOMAIN_EDMAC_2_RD_S1_B        |
| 0x213 | EDOMAIN_OPTI_RICH_A            |
| 0x214 | EDOMAIN_OPERA_ERR1             |
| 0x215 | ORCA_B_14                      |
| 0x216 | DOLPHIN_IRQ_DOLPHIN_1          |
| 0x217 | SIO2_SIO2INT                   |
| 0x218 | SYNC_IRQ_VIO_SET_3             |
| 0x219 | (reserved)                     |
| 0x21a | (reserved)                     |
| 0x21b | (reserved)                     |
| 0x21c | SROMC0_QUAD_OIRQ_TX            |
| 0x21d | SROMC1_OIRQ_TX                 |
| 0x21e | I2C0_RIRQ                      |
| 0x21f | MDOMAIN_5                      |
| 0x220 | EDOMAIN_EDMAC_1_WR_L2          |
| 0x221 | EDOMAIN_EDMAC_6_WR_SS2         |
| 0x222 | EDOMAIN_EDMAC_2_RD_S2_B        |
| 0x223 | EDOMAIN_OPTI_LITE_A            |
| 0x224 | EDOMAIN_OPERA_ABORT1           |
| 0x225 | ORCA_B_15                      |
| 0x226 | DOLPHIN_IRQ_DOLPHIN_2          |
| 0x227 | SIO3_SIO3INT                   |
| 0x228 | (reserved)                     |
| 0x229 | (reserved)                     |
| 0x22a | (reserved)                     |
| 0x22b | (reserved)                     |
| 0x22c | SROMC0_QUAD_OIRQ_RX            |
| 0x22d | SROMC1_OIRQ_RX                 |
| 0x22e | I2C0_SIRQ                      |
| 0x22f | MDOMAIN_6                      |
| 0x230 | EDOMAIN_EDMAC_1_WR_L3          |
| 0x231 | EDOMAIN_EDMAC_6_WR_SS3         |
| 0x232 | EDOMAIN_EDMAC_2_RD_S3_B        |
| 0x233 | EDOMAIN_OPTI_RICH_B            |
| 0x234 | EDOMAIN_HAIDI_PNL              |
| 0x235 | ORCA_B_16                      |
| 0x236 | DOLPHIN_IRQ_DOLPHIN_3          |
| 0x237 | SIO4_SIO4INT                   |
| 0x238 | (reserved)                     |
| 0x239 | (reserved)                     |
| 0x23a | HARB_HARBINT                   |
| 0x23b | RSTGEN_WDTINT                  |
| 0x23c | SROMC0_QUAD_OIRQ_FAULT         |
| 0x23d | SROMC1_OIRQ_FAULT              |
| 0x23e | I2C1_TIRQ                      |
| 0x23f | (reserved)                     |
| 0x240 | EDOMAIN_EDMAC_1_WR_L4          |
| 0x241 | EDOMAIN_EDMAC_6_WR_SS4         |
| 0x242 | EDOMAIN_EDMAC_3_RD_L0_A        |
| 0x243 | EDOMAIN_OPTI_LITE_B            |
| 0x244 | EDOMAIN_HAIDI_LINE             |
| 0x245 | ORCA_B_17                      |
| 0x246 | DOLPHIN_IRQ_DOLPHIN_4          |
| 0x247 | SIO5_SIO5INT                   |
| 0x248 | (reserved)                     |
| 0x249 | TSENS_IRQ_TSENS                |
| 0x24a | MCPU_DECERRINTR                |
| 0x24b | MCPU_L2CCINTR                  |
| 0x24c | SROMC0_QUAD_OERR_COLLECT       |
| 0x24d | SROMC1_OERR_COLLECT            |
| 0x24e | I2C1_RIRQ                      |
| 0x24f | (reserved)                     |
| 0x250 | EDOMAIN_EDMAC_1_WR_L5          |
| 0x251 | EDOMAIN_EDMAC_6_WR_SS5         |
| 0x252 | EDOMAIN_EDMAC_3_RD_L1_A        |
| 0x253 | EDOMAIN_JP52_1                 |
| 0x254 | EDOMAIN_HAIDI_EVF              |
| 0x255 | ORCA_B_18                      |
| 0x256 | GLDA                           |
| 0x257 | SIO6_SIO6INT                   |
| 0x258 | MARIO_0                        |
| 0x259 | DEBSIO                         |
| 0x25a | MCPU_ECNTRINTR                 |
| 0x25b | MCPU_PMUIRQ_0                  |
| 0x25c | INT_TM_MISC_CPU_HANDSHAKE0     |
| 0x25d | INT_TM_MISC_CPU_HANDSHAKE1     |
| 0x25e | I2C1_SIRQ                      |
| 0x25f | ADOMAIN                        |
| 0x260 | EDOMAIN_EDMAC_1_WR_M0          |
| 0x261 | EDOMAIN_EDMAC_6_WR_SS6         |
| 0x262 | EDOMAIN_EDMAC_3_RD_S0_A        |
| 0x263 | EDOMAIN_JP52_2                 |
| 0x264 | (reserved)                     |
| 0x265 | DMA330_ABORT                   |
| 0x266 | XIMR                           |
| 0x267 | SIO7_SIO7INT                   |
| 0x268 | MARIO_1                        |
| 0x269 | MCPU_SCUEVABORT                |
| 0x26a | MCPU_SLVERRINTR                |
| 0x26b | MCPU_PMUIRQ_1                  |
| 0x26c | MONI_MONIOUT_0                 |
| 0x26d | MONI_MONIOUT_1                 |
| 0x26e | MONI_MONIOUT_2                 |
| 0x26f | MONI_MONIOUT_3                 |
| 0x270 | INTC_ANDINT_0_0                |
| 0x271 | INTC_ANDINT_0_1                |
| 0x272 | INTC_ANDINT_0_2                |
| 0x273 | INTC_ANDINT_0_3                |
| 0x274 | INTC_ANDINT_0_4                |
| 0x275 | INTC_ANDINT_0_5                |
| 0x276 | (reserved)                     |
| 0x277 | (reserved)                     |
| 0x278 | (reserved)                     |
| 0x279 | (reserved)                     |
| 0x27a | INTC_ANDINT_1_0                |
| 0x27b | INTC_ANDINT_1_1                |
| 0x27c | INTC_ANDINT_1_2                |
| 0x27d | INTC_ANDINT_1_3                |
| 0x27e | INTC_ANDINT_1_4                |
| 0x27f | INTC_ANDINT_1_5                |


==== Interrupt Vector Table for GIC (Generic Interrupt Controller): ====

^ Vector ^ Description ^
| 0x280 | GIC_SGI(0)                     |
| 0x281 | GIC_SGI(1)                     |
| 0x282 | GIC_SGI(2)                     |
| 0x283 | GIC_SGI(3)                     |
| 0x284 | GIC_SGI(4)                     |
| 0x285 | GIC_SGI(5)                     |
| 0x286 | GIC_SGI(6)                     |
| 0x287 | GIC_SGI(7)                     |
| 0x288 | GIC_SGI(8)                     |
| 0x289 | GIC_SGI(9)                     |
| 0x28a | GIC_scheduling                 |
| 0x28b | GIC_timer                      |
| 0x28c | GIC_suspend                    |
| 0x28d | GIC_SGI(13)                    |
| 0x28e | GIC_SGI(14)                    |
| 0x28f | GIC_SGI(15)                    |
| 0x290 | GIC_PPI(16)                    |
| 0x291 | GIC_PPI(17)                    |
| 0x292 | GIC_PPI(18)                    |
| 0x293 | GIC_PPI(19)                    |
| 0x294 | GIC_PPI(20)                    |
| 0x295 | GIC_PPI(21)                    |
| 0x296 | GIC_PPI(22)                    |
| 0x297 | GIC_PPI(23)                    |
| 0x298 | GIC_PPI(24)                    |
| 0x299 | GIC_PPI(25)                    |
| 0x29a | GIC_PPI(26)                    |
| 0x29b | GIC_GlobalTimer                |
| 0x29c | GIC_LegacyFiq                  |
| 0x29d | GIC_PrivateTimer               |
| 0x29e | GIC_WatchdogTimer              |
| 0x29f | GIC_LegacyIrq                  |
| 0x2a0 | GIC_MariusIntc                 |
| 0x2a1 | GIC_OmarIntc                   |
| 0x2a2 | GIC_SPI(34)                    |
| 0x2a3 | GIC_SPI(35)                    |
| 0x2a4 | GIC_SPI(36)                    |
| 0x2a5 | GIC_SPI(37)                    |
| 0x2a6 | GIC_SPI(38)                    |
| 0x2a7 | GIC_SPI(39)                    |
| 0x2a8 | GIC_SPI(40)                    |
| 0x2a9 | GIC_SPI(41)                    |
| 0x2aa | GIC_SPI(42)                    |
| 0x2ab | GIC_SPI(43)                    |
| 0x2ac | GIC_SPI(44)                    |
| 0x2ad | GIC_SPI(45)                    |
| 0x2ae | GIC_SPI(46)                    |
| 0x2af | GIC_SPI(47)                    |
| 0x2b0 | GIC_SPI(48)                    |
| 0x2b1 | GIC_SPI(49)                    |
| 0x2b2 | GIC_SPI(50)                    |
| 0x2b3 | GIC_SPI(51)                    |
| 0x2b4 | GIC_SPI(52)                    |
| 0x2b5 | GIC_SPI(53)                    |
| 0x2b6 | GIC_SPI(54)                    |
| 0x2b7 | GIC_SPI(55)                    |
| 0x2b8 | GIC_SPI(56)                    |
| 0x2b9 | GIC_SPI(57)                    |
| 0x2ba | GIC_SPI(58)                    |
| 0x2bb | GIC_SPI(59)                    |
| 0x2bc | GIC_SPI(60)                    |
| 0x2bd | GIC_SPI(61)                    |
| 0x2be | GIC_SPI(62)                    |
| 0x2bf | GIC_SPI(63)                    |