====== DIGIC 7 ======

===== Interrupt Vector Table: =====

^ Vector ^ Description ^
| 0x000 | -noise-                                  |
| 0x001 | EDOMAIN_WR_L0                            |
| 0x002 | EDOMAIN_WR_SHREK                         |
| 0x003 | EDOMAIN_VECKY                            |
| 0x004 | EDOMAIN_AF_COMPLETE                      |
| 0x005 | EDOMAIN_MOSSY_0                          |
| 0x006 | SYNC_irq_intb60v                         |
| 0x007 | SYNC_irq_vi3_set_1                       |
| 0x008 | TMU_int_SWA                              |
| 0x009 | TMU_int_pulc                             |
| 0x00a | INTC_XINT *IRQEXT                        |
| 0x00b | TCU_T0OUT *IRQEXT                        |
| 0x00c | postman_RCVINT0                          |
| 0x00d | postman_FIFOINT0                         |
| 0x00e | Eeko_TIMER_OC0_INT                       |
| 0x00f | Eeko_TIMER_IC0_INT                       |
| 0x010 | EDOMAIN_HEAD_1                           |
| 0x011 | EDOMAIN_WR_L1                            |
| 0x012 | EDOMAIN_RD_OPT                           |
| 0x013 | EDOMAIN_SARIDON                          |
| 0x014 | EDOMAIN_AF_OVER_RUN_ERROR                |
| 0x015 | EDOMAIN_MOSSY_1                          |
| 0x016 | SYNC_irq_intb59v                         |
| 0x017 | SYNC_irq_vi3_set_2                       |
| 0x018 | TMU_int_SWB                              |
| 0x019 | TMU_int_occh0SP                          |
| 0x01a | INTC_XINT *IRQEXT                        |
| 0x01b | TCU_T1OUT *IRQEXT                        |
| 0x01c | postman_RCVINT1                          |
| 0x01d | postman_FIFOINT1                         |
| 0x01e | Eeko_TIMER_OC1_INT                       |
| 0x01f | Eeko_TIMER_IC1_INT                       |
| 0x020 | EDOMAIN_HEAD_2                           |
| 0x021 | EDOMAIN_WR_L2                            |
| 0x022 | EDOMAIN_RD_M0                            |
| 0x023 | EDOMAIN_INTR_MESSI                       |
| 0x024 | EDOMAIN_WB_BLOCK                         |
| 0x025 | EDOMAIN_MOSSY_2                          |
| 0x026 | SYNC_irq_intb50v                         |
| 0x027 | SYNC_irq_vi3_set_3                       |
| 0x028 | TMU_int_ocall                            |
| 0x029 | TMU_int_occh0EP                          |
| 0x02a | INTC_XINT *IRQEXT                        |
| 0x02b | TCU_T2OUT *IRQEXT                        |
| 0x02c | postman_RCVINT2                          |
| 0x02d | postman_FIFOINT2                         |
| 0x02e | Eeko_TIMER_OC2_INT                       |
| 0x02f | Eeko_TIMER_IC2_INT                       |
| 0x030 | EDOMAIN_HEAD_3                           |
| 0x031 | EDOMAIN_WR_M0                            |
| 0x032 | EDOMAIN_RD_M1                            |
| 0x033 | EDOMAIN_FENCING_B(INTR_DAN_FB)           |
| 0x034 | EDOMAIN_WB_AE                            |
| 0x035 | EDOMAIN_MOSSY_3                          |
| 0x036 | SYNC_irq_intb49v                         |
| 0x037 | SYNC_irq_intvi4                          |
| 0x038 | TMU_int_pulgenCEI                        |
| 0x039 | TMU_int_occh1SP                          |
| 0x03a | INTC_XINT *IRQEXT                        |
| 0x03b | TCU_T3OUT *IRQEXT                        |
| 0x03c | postman_RCVINT3                          |
| 0x03d | postman_FIFOINT3                         |
| 0x03e | Eeko_TIMER_OC3_INT                       |
| 0x03f | Eeko_TIMER_IC3_INT                       |
| 0x040 | EDOMAIN_HEAD_4                           |
| 0x041 | EDOMAIN_WR_M1                            |
| 0x042 | EDOMAIN_RD_M2                            |
| 0x043 | EDOMAIN_INTR_DAN_RA                      |
| 0x044 | EDOMAIN_WEABER1                          |
| 0x045 | EDOMAIN_MOSSY_4                          |
| 0x046 | SYNC_irq_intl60v                         |
| 0x047 | SYNC_irq_vi4_set_1                       |
| 0x048 | TMU_int_icapCE1                          |
| 0x049 | TMU_int_occh1EP                          |
| 0x04a | INTC_XINT *IRQEXT                        |
| 0x04b | TCU_T4OUT *IRQEXT                        |
| 0x04c | postman_RCVINT4                          |
| 0x04d | postman_FIFOINT4                         |
| 0x04e | Eeko_TIMER_OC4_INT                       |
| 0x04f | Eeko_TIMER_IC4_INT                       |
| 0x050 | EDOMAIN_HEAD_FRM                         |
| 0x051 | EDOMAIN_WR_M2                            |
| 0x052 | EDOMAIN_RD_M3                            |
| 0x053 | EDOMAIN_INTR_DAN_BB                      |
| 0x054 | EDOMAIN_WEABER2                          |
| 0x055 | EDOMAIN_MOSSY_5                          |
| 0x056 | SYNC_irq_intl59v                         |
| 0x057 | SYNC_irq_vi4_set_2                       |
| 0x058 | TMU_pulc_ch0                             |
| 0x059 | TMU_int_occh2SP                          |
| 0x05a | INTC_XINT *IRQEXT                        |
| 0x05b | TCU_T5OUT *IRQEXT                        |
| 0x05c | postman_RCVINT5                          |
| 0x05d | postman_FIFOINT5                         |
| 0x05e | Eeko_TIMER_OC5_INT                       |
| 0x05f | Eeko_TIMER_IC5_INT                       |
| 0x060 | EDOMAIN_HEAD_STP                         |
| 0x061 | EDOMAIN_WR_M3                            |
| 0x062 | EDOMAIN_RD_M4                            |
| 0x063 | EDOMAIN_INTR_DAN_SU                      |
| 0x064 | lime_IntX_A0                             |
| 0x065 | EDOMAIN_HBUS_ERROR                       |
| 0x066 | SYNC_irq_intl50v                         |
| 0x067 | SYNC_irq_vi4_set_3                       |
| 0x068 | TMU_pulc_ch1                             |
| 0x069 | TMU_int_occh2EP                          |
| 0x06a | INTC_XINT *IRQEXT                        |
| 0x06b | TCU_IPCOUT4                              |
| 0x06c | postman_RCVINT6                          |
| 0x06d | postman_FIFOINT6                         |
| 0x06e | Eeko_TIMER_OC6_INT                       |
| 0x06f | Eeko_TIMER_IC6_INT                       |
| 0x070 | EDOMAIN_HEAD_ERROR                       |
| 0x071 | EDOMAIN_WR_M4                            |
| 0x072 | EDOMAIN_RD_M5                            |
| 0x073 | EDOMAIN_SMAP                             |
| 0x074 | lime_IntX_A1                             |
| 0x075 | EDOMAIN_EEKO_ERROR                       |
| 0x076 | SYNC_irq_intlssdv                        |
| 0x077 | SYNC_irq_intvio                          |
| 0x078 | TMU_pulc_ch2                             |
| 0x079 | TMU_int_occh3SP                          |
| 0x07a | INTC_XINT *IRQEXT                        |
| 0x07b | TCU_T4F_INT                              |
| 0x07c | postman_RCVINT7                          |
| 0x07d | postman_FIFOINT7                         |
| 0x07e | Eeko_TIMER_OC7_INT                       |
| 0x07f | Eeko_TIMER_IC7_INT                       |
| 0x080 | EDOMAIN_HEAD_ERROR2                      |
| 0x081 | EDOMAIN_WR_M5                            |
| 0x082 | EDOMAIN_RD_M6                            |
| 0x083 | EDOMAIN_HIST_COMPLETE                    |
| 0x084 | lime_IntX_A_NF0                          |
| 0x085 | EDOMAIN_reserve                          |
| 0x086 | SYNC_irq_intp1                           |
| 0x087 | SYNC_irq_vio_set_1                       |
| 0x088 | TMU_pulc_ch3                             |
| 0x089 | TMU_int_occh3EP                          |
| 0x08a | INTC_XINT *IRQEXT                        |
| 0x08b | TCU_IPCOUT5                              |
| 0x08c | postman_DIRECTINT0                       |
| 0x08d | postman_Semaphore0                       |
| 0x08e | Eeko_TIMER_ICOC_OC0INT                   |
| 0x08f | Eeko_TIMER_ICOC_IC0INT                   |
| 0x090 | EDOMAIN_DEF(PREPRO1)                     |
| 0x091 | EDOMAIN_WR_S_A0                          |
| 0x092 | EDOMAIN_RD_M7                            |
| 0x093 | EDOMAIN_HIST2_1                          |
| 0x094 | lime_IntX_A_NF1                          |
| 0x095 | EDOMAIN_reserve                          |
| 0x096 | SYNC_irq_intp1_st1                       |
| 0x097 | SYNC_irq_vio_set_2                       |
| 0x098 | Camif                                    |
| 0x099 | TMU_int_occh4SP                          |
| 0x09a | INTC_XINT *IRQEXT                        |
| 0x09b | TCU_T5F_INT                              |
| 0x09c | postman_DIRECTINT1                       |
| 0x09d | postman_Semaphore1                       |
| 0x09e | Eeko_TIMER_ICOC_OC1INT                   |
| 0x09f | Eeko_TIMER_ICOC_IC1INT                   |
| 0x0a0 | EDOMAIN_BEATON(PREPRO2)                  |
| 0x0a1 | EDOMAIN_WR_S_A1                          |
| 0x0a2 | EDOMAIN_RD_S_A0                          |
| 0x0a3 | EDOMAIN_HIST2_2                          |
| 0x0a4 | PCIe_INTA_RC                             |
| 0x0a5 | EDOMAIN_reserve                          |
| 0x0a6 | SYNC_irq_intc1                           |
| 0x0a7 | SYNC_irq_vio_set_3                       |
| 0x0a8 | Camif                                    |
| 0x0a9 | TMU_int_occh4EP                          |
| 0x0aa | INTC_XINT *IRQEXT                        |
| 0x0ab | Aproc_irq_aproc                          |
| 0x0ac | postman_DIRECTINT2                       |
| 0x0ad | postman_Semaphore2                       |
| 0x0ae | dengen_irq_dengen*IRQEXT                 |
| 0x0af | zico_timer_irq                           |
| 0x0b0 | EDOMAIN_PREPRO3                          |
| 0x0b1 | EDOMAIN_WR_S_A2                          |
| 0x0b2 | EDOMAIN_RD_S_A1                          |
| 0x0b3 | EDOMAIN_HIST2_3                          |
| 0x0b4 | PCIe_INTB_RC                             |
| 0x0b5 | TMU_INT_SWA_ONLY                         |
| 0x0b6 | SYNC_irq_intc1_st1                       |
| 0x0b7 | SYNC_irq_intvi5                          |
| 0x0b8 | Camif                                    |
| 0x0b9 | TMU_int_occh5SP                          |
| 0x0ba | INTC_XINT *IRQEXT                        |
| 0x0bb | Aproc_irq_aproc                          |
| 0x0bc | postman_DIRECTINT3                       |
| 0x0bd | postman_Semaphore3                       |
| 0x0be | SDDomain_ADMAC0                          |
| 0x0bf | HDMAC0_IntrReq2                          |
| 0x0c0 | EDOMAIN_WB_INTG                          |
| 0x0c1 | EDOMAIN_WR_S_A3                          |
| 0x0c2 | EDOMAIN_RD_S_A2                          |
| 0x0c3 | EDOMAIN_HIST2_4                          |
| 0x0c4 | PCIe_INTC_RC                             |
| 0x0c5 | TMU_INT_SWB_ONLY                         |
| 0x0c6 | SYNC_irq_intc2                           |
| 0x0c7 | SYNC                                     |
| 0x0c8 | Camif_DEBSIO                             |
| 0x0c9 | TMU_int_occh5EP                          |
| 0x0ca | INTC_XINT *IRQEXT                        |
| 0x0cb | Aproc_irq_aproc                          |
| 0x0cc | postman_DIRECTINT4                       |
| 0x0cd | postman_fifi_err0                        |
| 0x0ce | SDDomain_ADMAC1                          |
| 0x0cf | HDMAC0_IntrReq3                          |
| 0x0d0 | EDOMAIN_HEAD_ERROR4                      |
| 0x0d1 | EDOMAIN_WR_S_A4                          |
| 0x0d2 | EDOMAIN_RD_S_A3                          |
| 0x0d3 | EDOMAIN_KAISER                           |
| 0x0d4 | PCIe_INTD_RC                             |
| 0x0d5 | TMU_INT_SWC_ONLY                         |
| 0x0d6 | SYNC_irq_intc2_st1                       |
| 0x0d7 | SYNC                                     |
| 0x0d8 | Camif                                    |
| 0x0d9 | TMU_int_icapch0                          |
| 0x0da | INTC_XINT *IRQEXT                        |
| 0x0db | Aproc_irq_aproc                          |
| 0x0dc | postman_DIRECTINT5                       |
| 0x0dd | I2C1_IICBTIA *IRQEXT                     |
| 0x0de | SDDomain_ADMAC2                          |
| 0x0df | HDMAC0_IntrReq6                          |
| 0x0e0 | EDOMAIN_HEAD_ERROR5                      |
| 0x0e1 | EDOMAIN_WR_S_A5                          |
| 0x0e2 | EDOMAIN_RD_S_A4                          |
| 0x0e3 | EDOMAIN_CAPTAIN                          |
| 0x0e4 | PCIe_INTMSI_RC                           |
| 0x0e5 | TMU_INT_SWD_ONLY                         |
| 0x0e6 | SYNC_irq_lss                             |
| 0x0e7 | XIMR                                     |
| 0x0e8 | Camif                                    |
| 0x0e9 | TMU_int_icapch1                          |
| 0x0ea | INTC_XINT *IRQEXT                        |
| 0x0eb | Aproc_irq_aproc                          |
| 0x0ec | postman_DIRECTINT6                       |
| 0x0ed | I2C1_IICBTIS *IRQEXT                     |
| 0x0ee | SDDomain_SDCON0                          |
| 0x0ef | HDMAC0_IntrReq7                          |
| 0x0f0 | EDOMAIN_HEAD_1_A                         |
| 0x0f1 | EDOMAIN_WR_S_A6                          |
| 0x0f2 | EDOMAIN_RD_S_B0                          |
| 0x0f3 | EDOMAIN_EBIKE                            |
| 0x0f4 | PCIe_AXI_ERR_INT                         |
| 0x0f5 | GLDA                                     |
| 0x0f6 | SYNC_irq_intlss_st1                      |
| 0x0f7 | XIMR                                     |
| 0x0f8 | Camif                                    |
| 0x0f9 | TMU_int_icapch2                          |
| 0x0fa | INTC_XINT *IRQEXT                        |
| 0x0fb | Aproc_irq_aproc                          |
| 0x0fc | postman_DIRECTINT7                       |
| 0x0fd | I2C2_IICBTIA *IRQEXT                     |
| 0x0fe | SDDomain_SDCON1                          |
| 0x0ff | IPC_IPC_INT                              |
| 0x100 | EDOMAIN_HEAD_2_A                         |
| 0x101 | EDOMAIN_WR_S_B0                          |
| 0x102 | EDOMAIN_RD_S_B1                          |
| 0x103 | EDOMAIN_JP52                             |
| 0x104 | PCIe_PCIE_EVT_INT                        |
| 0x105 | Checksum_intr                            |
| 0x106 | SYNC_irq_intvi1                          |
| 0x107 | SSIO_SSIOINT                             |
| 0x108 | Camif                                    |
| 0x109 | TMU_int_icapch3                          |
| 0x10a | INTC_XINT *IRQEXT                        |
| 0x10b | Aproc_irq_aproc                          |
| 0x10c | BLTDMAC_bltdmaInt_0                      |
| 0x10d | I2C2_IICBTIS *IRQEXT                     |
| 0x10e | SDDomain_SDCON2                          |
| 0x10f | a2i_cache (ZICO)_irq_a2i(2)              |
| 0x110 | EDOMAIN_PEPPER_SB                        |
| 0x111 | EDOMAIN_WR_S_B1                          |
| 0x112 | EDOMAIN_RD_S_B2                          |
| 0x113 | EDOMAIN_SUSAN_1                          |
| 0x114 | PCIe_MSG_INT                             |
| 0x115 | Camif_ADFB_INT                           |
| 0x116 | SYNC_irq_vi1_set_1                       |
| 0x117 | SIO0_SIO0INT                             |
| 0x118 | Camif                                    |
| 0x119 | TMU_int_icapch4                          |
| 0x11a | INTC_XINT *IRQEXT                        |
| 0x11b | Aproc_irq_aproc                          |
| 0x11c | BLTDMAC_bltdmaInt_1                      |
| 0x11d | RSTGEN_WDTINT                            |
| 0x11e | XDMAC_DMAEND                             |
| 0x11f | DEBSIO                                   |
| 0x120 | EDOMAIN_DAFIGARO                         |
| 0x121 | EDOMAIN_WR_S_B2                          |
| 0x122 | EDOMAIN_RD_S_C0                          |
| 0x123 | EDOMAIN_SUSAN_2                          |
| 0x124 | PCIe_INT_PM_PME                          |
| 0x125 | Camif_ADB_INT                            |
| 0x126 | SYNC_irq_vi1_set_2                       |
| 0x127 | SIO1_SIO1INT                             |
| 0x128 | Camif                                    |
| 0x129 | TMU_int_icapch5                          |
| 0x12a | INTC_XINT *IRQEXT                        |
| 0x12b | Aproc_irq_aproc                          |
| 0x12c | BLTDMAC_bltdmaInt_2                      |
| 0x12d | USB_U2H_BIND_INT                         |
| 0x12e | XDMAC_DMAEND                             |
| 0x12f | rem_REM_INT                              |
| 0x130 | EDOMAIN_HEAD_3_A                         |
| 0x131 | EDOMAIN_WR_S_B3                          |
| 0x132 | EDOMAIN_RD_S_C1                          |
| 0x133 | EDOMAIN_SUSAN_3                          |
| 0x134 | PCIe_INT_SERR                            |
| 0x135 | i2i_dmac_irq_i2i                         |
| 0x136 | SYNC_irq_vi1_set_3                       |
| 0x137 | SIO2_SIO2INT                             |
| 0x138 | Camif                                    |
| 0x139 | TMU_int_icapch6                          |
| 0x13a | INTC_XINT *IRQEXT                        |
| 0x13b | Aproc_irq_aproc                          |
| 0x13c | BLTDMAC_bltdmaInt_3                      |
| 0x13d | USB_U2D_BIND_INT *IRQEXT                 |
| 0x13e | XDMAC_DMAEND                             |
| 0x13f | BUZ_BUZINT                               |
| 0x140 | EDOMAIN_HEAD_4_A                         |
| 0x141 | EDOMAIN_WR_S_C0                          |
| 0x142 | EDOMAIN_RD_S_C2                          |
| 0x143 | EDOMAIN_OHYEAR                           |
| 0x144 | PCIe_INT_ALL                             |
| 0x145 | i2i_dmac_irq_i2i                         |
| 0x146 | SYNC_irq_intvi2                          |
| 0x147 | SIO3_SIO3INT                             |
| 0x148 | Camif                                    |
| 0x149 | TMU_int_icapch7                          |
| 0x14a | INTC_XINT *IRQEXT                        |
| 0x14b | INTC_XINT *IRQEXT                        |
| 0x14c | BLTDMAC_bltdmaInt_4                      |
| 0x14d | USB_U2_ERR_BIND_INT*IRQEXT               |
| 0x14e | XDMAC_DMAEND                             |
| 0x14f | SROMC2_ERR_INT *IRQEXT                   |
| 0x150 | EDOMAIN_HEAD_FRM_A                       |
| 0x151 | EDOMAIN_WR_S_C1                          |
| 0x152 | EDOMAIN_RD_S_C3                          |
| 0x153 | EDOMAIN_OPTIMUS                          |
| 0x154 | PCIe_DMA_INT                             |
| 0x155 | i2i_dmac_irq_i2i                         |
| 0x156 | SYNC_irq_vi2_set_1                       |
| 0x157 | SIO4_SIO4INT                             |
| 0x158 | Camif                                    |
| 0x159 | TMU_int_icapch8                          |
| 0x15a | INTC_XINT *IRQEXT                        |
| 0x15b | INTC_XINT *IRQEXT                        |
| 0x15c | BLTDMAC_bltdmaInt_5                      |
| 0x15d | UART0 RX_IntReqRx                        |
| 0x15e | XDMAC_DMAEND                             |
| 0x15f | SROMC2_INTAHBERR *IRQEXT                 |
| 0x160 | EDOMAIN_HEAD_STP_A                       |
| 0x161 | EDOMAIN_WR_S_C2                          |
| 0x162 | EDOMAIN_RD_S_C4                          |
| 0x163 | EDOMAIN_OPTIMUS2                         |
| 0x164 | GRPH                                     |
| 0x165 | dlphn                                    |
| 0x166 | SYNC_irq_vi2_set_2                       |
| 0x167 | SIO5_SIO5INT                             |
| 0x168 | Camif                                    |
| 0x169 | TMU_int_icapch9                          |
| 0x16a | INCT_XINT *IRQEXT                        |
| 0x16b | INCT_XINT *IRQEXT                        |
| 0x16c | BLTDMAC_bltdmaInt_6                      |
| 0x16d | UART0 TX_IntReqTx                        |
| 0x16e | XDMAC_DMAEND                             |
| 0x16f | SROMC2_INTR                              |
| 0x170 | EDOMAIN_SHREK1                           |
| 0x171 | EDOMAIN_WR_S_C3                          |
| 0x172 | EDOMAIN_RD_S_C5                          |
| 0x173 | EDOMAIN_DISTER                           |
| 0x174 | GRPH                                     |
| 0x175 | dlphn                                    |
| 0x176 | SYNC_irq_vi2_set_3                       |
| 0x177 | SIO6_SIO6INT                             |
| 0x178 | SMACKY                                   |
| 0x179 | TMU_int_icapch10                         |
| 0x17a | INTC_XINT *IRQEXT                        |
| 0x17b | INTC_XINT *IRQEXT                        |
| 0x17c | BLTDMAC_bltdmaInt_7                      |
| 0x17d | UART1 RX_IntReqRx                        |
| 0x17e | XDMAC_DMAEND                             |
| 0x17f | SROMC1_ERR_INT *IRQEXT                   |
| 0x180 | EDOMAIN_SHREK2                           |
| 0x181 | EDOMAIN_WR_S_C4                          |
| 0x182 | EDOMAIN_RD_S_C6                          |
| 0x183 | EDOMAIN_DISTER2                          |
| 0x184 | sod_io_lime_lime_dat_in0_1_lime *IRQEXT  |
| 0x185 | a2i_limeid0_int                          |
| 0x186 | SYNC_irq_intvi3                          |
| 0x187 | SIO7_SIO7INT                             |
| 0x188 | SMACKY                                   |
| 0x189 | TMU_int_icapch11                         |
| 0x18a | ADOMAIN_MISC_HANDSHAKE0                  |
| 0x18b | lime_intX_A2                             |
| 0x18c | lime_int_xdpw1                           |
| 0x18d | UART1 TX_IntReqTx                        |
| 0x18e | XDMAC_DMAEND                             |
| 0x18f | SROMC1_INTAHBERR *IRQEXT                 |
| 0x190 | EDOMAIN_BAUST                            |
| 0x191 | EDOMAIN_WR_S_C5                          |
| 0x192 | EDOMAIN_RD_DAN                           |
| 0x193 | EDOMAIN_WR_DAN                           |
| 0x194 | sod_io_lime_lime_dat_in1_1_lime *IRQEXT  |
| 0x195 | a2i_limeid2_int                          |
| 0x196 | PCIe_INT_SERR_COR                        |
| 0x197 | INTC_IRQ_soft_out                        |
| 0x198 | SMACKY                                   |
| 0x199 | AIC_h2a_int                              |
| 0x19a | ADOMAIN_MISC_HANDSHAKE1                  |
| 0x19b | lime_INTX_A_NF2                          |
| 0x19c | lime_int_xdpw1                           |
| 0x19d | main_cpu_ss_L2CCINTR                     |
| 0x19e | XDMAC_DMAERR                             |
| 0x19f | SROMC1_INTR                              |
| 0x1a0 | INTC_ANDINT(0)                           |
| 0x1a1 | INTC_ANDINT(1)                           |
| 0x1a2 | INTC_ANDINT(2)                           |
| 0x1a3 | INTC_ANDINT(3)                           |
| 0x1a4 | INTC_ANDINT(4)                           |
| 0x1a5 | INTC_ANDINT(5)                           |
| 0x1a6 | PCIe_INT_SERR_NONFATAL                   |
| 0x1a7 | lime_int_citron                          |
| 0x1a8 | lime_int_xdmac                           |
| 0x1a9 | lime_int_sdcon                           |
| 0x1aa | INTC_ANDINT(0)                           |
| 0x1ab | INTC_ANDINT(1)                           |
| 0x1ac | INTC_ANDINT(2)                           |
| 0x1ad | INTC_ANDINT(3)                           |
| 0x1ae | INTC_ANDINT(4)                           |
| 0x1af | INTC_ANDINT(5)                           |
| 0x1b0 | main_cpu_ss_SCUEVABORT*IRQEXT            |
| 0x1b1 | main_cpu_ss_DECERRINTR                   |
| 0x1b2 | main_cpu_ss_ECNTRINTR                    |
| 0x1b3 | main_cpu_ss_SLVERRINTR                   |
| 0x1b4 | main_cpu_ss_PMUIRQ                       |
| 0x1b5 | main_cpu_ss_PMUIRQ                       |
| 0x1b6 | PCIe_INT_SERR_FATAL                      |
| 0x1b7 |                                          |
| 0x1b8 | dengen_irq_dengen*IRQEXT                 |
| 0x1b9 | AXI2APB IC_ERR_INT*IRQEXT                |
| 0x1ba | AXI2APB IC_AHBERR*IRQEXT                 |
| 0x1bb | harb_harbInt                             |
| 0x1bc | MONI_moniout(0)*IRQEXT                   |
| 0x1bd | MONI_moniout(1)*IRQEXT                   |
| 0x1be | MONI_moniout(2)*IRQEXT                   |
| 0x1bf | MONI_moniout(3)*IRQEXT                   |

==== Interrupt Vector Table for GIC (Generic Interrupt Controller): ====

^ Vector ^ Description ^
| 0x1c0 | GIC_SGI(0)                               |
| 0x1c1 | GIC_SGI(1)                               |
| 0x1c2 | GIC_SGI(2)                               |
| 0x1c3 | GIC_SGI(3)                               |
| 0x1c4 | GIC_SGI(4)                               |
| 0x1c5 | GIC_SGI(5)                               |
| 0x1c6 | GIC_SGI(6)                               |
| 0x1c7 | GIC_SGI(7)                               |
| 0x1c8 | GIC_SGI(8)                               |
| 0x1c9 | GIC_SGI(9)                               |
| 0x1ca | GIC_scheduling                           |
| 0x1cb | GIC_timer                                |
| 0x1cc | GIC_suspend                              |
| 0x1cd | GIC_SGI(13) on 200D this is used to suspend other CPUs |
| 0x1ce | GIC_SGI(14)                              |
| 0x1cf | GIC_SGI(15)                              |
| 0x1d0 | GIC_PPI(16)                              |
| 0x1d1 | GIC_PPI(17)                              |
| 0x1d2 | GIC_PPI(18)                              |
| 0x1d3 | GIC_PPI(19)                              |
| 0x1d4 | GIC_PPI(20)                              |
| 0x1d5 | GIC_PPI(21)                              |
| 0x1d6 | GIC_PPI(22)                              |
| 0x1d7 | GIC_PPI(23)                              |
| 0x1d8 | GIC_PPI(24)                              |
| 0x1d9 | GIC_PPI(25)                              |
| 0x1da | GIC_PPI(26)                              |
| 0x1db | GIC_GlobalTimer                          |
| 0x1dc | GIC_LegacyFiq                            |
| 0x1dd | GIC_PrivateTimer                         |
| 0x1de | GIC_WatchdogTimer                        |
| 0x1df | GIC_LegacyIrq                            |
| 0x1e0 | GIC_MariusIntc                           |
| 0x1e1 | GIC_OmarIntc                             |
| 0x1e2 | GIC_SPI(34)                              |
| 0x1e3 | GIC_SPI(35)                              |
| 0x1e4 | GIC_SPI(36)                              |
| 0x1e5 | GIC_SPI(37)                              |
| 0x1e6 | GIC_SPI(38)                              |
| 0x1e7 | GIC_SPI(39)                              |
| 0x1e8 | GIC_SPI(40)                              |
| 0x1e9 | GIC_SPI(41)                              |
| 0x1ea | GIC_SPI(42)                              |
| 0x1eb | GIC_SPI(43)                              |
| 0x1ec | GIC_SPI(44)                              |
| 0x1ed | GIC_SPI(45)                              |
| 0x1ee | GIC_SPI(46)                              |
| 0x1ef | GIC_SPI(47)                              |
| 0x1f0 | GIC_SPI(48)                              |
| 0x1f1 | GIC_SPI(49)                              |
| 0x1f2 | GIC_SPI(50)                              |
| 0x1f3 | GIC_SPI(51)                              |
| 0x1f4 | GIC_SPI(52)                              |
| 0x1f5 | GIC_SPI(53)                              |
| 0x1f6 | GIC_SPI(54)                              |
| 0x1f7 | GIC_SPI(55)                              |
| 0x1f8 | GIC_SPI(56)                              |
| 0x1f9 | GIC_SPI(57)                              |
| 0x1fa | GIC_SPI(58)                              |
| 0x1fb | GIC_SPI(59)                              |
| 0x1fc | GIC_SPI(60)                              |
| 0x1fd | GIC_SPI(61)                              |
| 0x1fe | GIC_SPI(62)                              |
| 0x1ff | GIC_SPI(63)                              |